Datasheet

SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
FUNCTION TABLE
INPUTS OUTPUTS
CLR CLK A B Q
A
Q
B
...Q
H
L X X X L L L
H LXXQ
A0
Q
B0
Q
H0
H ↑ HHHQ
An
Q
Gn
H ↑ LXLQ
An
Q
Gn
H ↑ X L L Q
An
Q
Gn
Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
, or Q
H
, respectively,
before the indicated steady-state input conditions were
established
Q
An
, Q
Gn
= the level of Q
A
or Q
G
before the most recent
↑ transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
9
A
B
CLR
CLK
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
C1
1D
R
3
Q
A
C1
1D
R
4
Q
B
C1
1D
R
5
Q
C
C1
1D
R
6
Q
D
C1
1D
R
10
Q
E
C1
1D
R
11
Q
F
C1
1D
R
12
Q
G
C1
1D
R
13
Q
H
2
1
8