Datasheet
9
A
B
CLR
CLK
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
C1
1D
R
3
Q
A
C1
1D
R
4
Q
B
C1
1D
R
5
Q
C
C1
1D
R
6
Q
D
C1
1D
R
10
Q
E
C1
1D
R
11
Q
F
C1
1D
R
12
Q
G
C1
1D
R
13
Q
H
2
1
8
SN54HC164
,
SN74HC164
SCLS115G –DECEMBER 1982 –REVISED SEPTEMBER 2015
www.ti.com
9 Detailed Description
9.1 Overview
The SN74HC164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well
as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data
line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK
is high or low, provided that the minimum set-up time requirements are met.
The CLK pin of the SN74HC164 is triggered on a positive or rising-edge signal, from LOW to HIGH. Upon a
positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and
propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each
clock trigger. If a low signal is applied to the CLR pin of the SN74HC164, the device will set all registers to a
value of 0 immediately.
9.2 Functional Block Diagram
9.3 Feature Description
The HC164 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and
Low Power Consumption, 80-μA maximum I. It is typically t
pd
= 20 ns and has ±4-mA output drive at 5 V with low
input current of 1-μA maximum. It also has AND-gated (enable/disable) serial inputs a fully buffered clock and
serial inputs as well as a direct clear.
9.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4HC164.
Table 1. Function Table
(1)(2)
INPUTS OUTPUTS
CLR CLK A B Q
A
Q
B
. . . Q
H
L X X X L L L
H L X X Q
A0
Q
B0
Q
H0
H ↑ H H H Q
An
Q
Gn
H ↑ L X L Q
An
Q
Gn
H ↑ X L L Q
An
Q
Gn
(1) Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established.
(2) Q
An
, Q
Gn
= the level of Q
A
or Q
G
before the most recent ↑ transition
of CLK: indicates a 1-bit shift.
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Product Folder Links: SN54HC164 SN74HC164