Datasheet

M54HC10
M74HC10
December 1992
TRIPLE 3-INPUT NAND GATE
B1R
(Plastic Package)
ORDER CODES :
M54HC10F1R M74HC10M1R
M74HC10B1R M74HC10C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.HIGH SPEED
t
PD
= 6 ns (TYP.) AT V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=1µA (MAX.) AT T
A
=25°C
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
IOH =I
OL
= 4 mA (MIN.)
.BALANCED PROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE WITH
54/74LS10
The M54/74HC10 is a high speed CMOS TRIPLE
3-INPUT NAND GATE fabricated with silicon gate
C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
The internal circuit is composed of 3 stages includ-
ing buffer output, which enables high noise im-
munity and stable output.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
DESCRIPTION
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