Datasheet

SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286E – OCTOBER 1999 – REVISED AUGUST 2001
3–23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
OUTPUT CONTROL
INPUTS
T/C OEAB OEBY
OUTPUT MODE
X H H Z Isolation
H L H A data to B bus
H H L B data to Y bus
True transparent
H L L A data to B bus, B data to Y bus
True transparent with
feedback path
L L H Inverted A data to B bus
L H L Inverted B data to Y bus
Inverted transparent
L L L
Inverted A data to B bus,
Inverted B data to Y bus
Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT ERC
OUTPUT
LOGIC
LEVEL
NOMINAL
VOLTAGE
B-PORT
EDGE RATE
L GND Slow
H
V
CC
Fast
logic diagram (positive logic)
OEAB
T/C
OEBY
7
9
1
ERC
8
A1
5
Y1
2
V
REF
10
A2
6
Y2
3
B1
14
B2
12