Datasheet

Board Layouts and Schematics
7–383
Bill of Materials, Schematics, Board Layouts, and Suggested Specifications
Figure A–11. Clock-Card Schematic
Clock Card
A
11
Thursday, March 16, 2000
Title
Size Document Number
Rev
Date: Sheet of
3.3V 3.3V
3.3V
5V
3.3V
51.1
U1
TP1
R1
C1
.1uF
U2 U3
C3
.1uF .1uF
.1uF
C4
C5
.1uF
.1uF .1uF
.1uF
.1uF
C6 C7
C8
C9
J3
50 ohm lines. All clock
output lines to J3 are
the same length (5%)
C10
.1uF
R2
453
CLK_OUT1
CLK_OUT6
CLK_OUT9
CLK_OUT10
CLK_OUT16
CLK_OUT18
CLK_OUT4
CLK_OUT7
CLK_OUT15
CLK_OUT2
CLK_OUT5
CLK_OUT17
CLK_OUT19
CLK_OUT13
CLK_OUT3
CLK_OUT20
CLK_OUT8
CLK_OUT12
CLK_OUT11
CLK_OUT14
CDC2586
GND
1
1Y1
2
Vcc
3
GND
4
1Y2
5
Vcc
6
GND
7
1Y3
8
Vcc
9
GND
10
GND
11
2Y1
12
Vcc
13
GND
3Y3
Vcc
GND
GND
4Y1
Vcc
GND
4Y2
Vcc
GND
4Y3
Vcc
CLR
TEST
OE
Vcc
NC
CLKIN
Vcc
GND
FBIN
GND
SEL0
SEL1
GND
CDC2586
GND
1
1Y1
2
Vcc
3
GND
4
1Y2
5
Vcc
6
GND
7
1Y3
8
Vcc
9
GND
10
GND
11
2Y1
12
Vcc
13
GND
14
2Y2
15
Vcc
16
GND
17
2Y3
18
Vcc
19
GND
20
GND
21
3Y1
22
Vcc
23
GND
24
3Y2
25
Vcc
26
GND
27
3Y3
28
Vcc
29
GND
30
GND
31
4Y1
32
Vcc
33
GND
34
4Y2
35
Vcc
36
GND
37
4Y3
38
Vcc
39
CLR
40
TEST
41
OE
42
Vcc
43
NC
44
CLKIN
45
Vcc
46
GND
47
FBIN
48
GND
49
SEL0
50
SEL1
51
GND
52
Z– PAK (C)
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E3
E2
E4
E5
E6
E7
E8
E9
E10
E11
B1
B11
E1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B2
B3
B4
B5
B6
B7
B8
B9
B10
OSC
N/C
1
GND
4
OUT
5
Vcc
8
SMB
1
3
2
4
5
GND
2Y2
Vcc
GND
2Y3
Vcc
GND
GND
3Y1
Vcc
GND
3Y2
Vcc
40
41
42
43
44
45
46
47
48
49
50
51
52
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39