Datasheet
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
3–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D GTLP-to-LVTTL 1-to-6 Fanout Driver
D LVTTL-to-GTLP 1-to-2 Fanout Driver
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTLP Outputs (50 mA)
D Reduced-Drive LVTTL Outputs
(–12 mA/12 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
and Power-Up 3-State Support Hot
Insertion
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard
TTL or LVTTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input
threshold levels, improved differential input, and OEC circuitry. The improved GTLP OEC circuitry minimizes
bus settling time and has been designed and tested using several backplane models. The medium drive allows
incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. BO1 and
BO2 can be tied together to drive an equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLP817 is given only at the preferred higher noise-margin GTLP,
but the user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP
(V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
GNDT is the TTL output ground, while GNDG is the GTLP output ground, and both may be separated from each
other for a quieter device.
Copyright 2001, Texas Instruments Incorporated
DGV, DW, OR PW PACKAGE
(TOP VIEW)
AI
AO1
GNDT
AO2
V
CC
AO3
GNDT
AO4
V
CC
AO5
GNDT
AO6
GNDT
OEAB
BO1
GNDG
V
REF
GNDG
ERC
BO2
GNDG
BI
OEBA
GNDT
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2
3
4
5
6
7
8
9
10
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12
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OEC and TI are trademarks of Texas Instruments.