Datasheet

Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2)
7–356
4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and
Driver Card (D1) Latch Clock (Ch2)
Figure 4–1 shows the probe hookup and related O-Scope output for Case 1.
The LVTTL latch clock signal goes to the SN74GTLPH1655 driving device
CLK pin, and the LVTTL data signal goes to the A-port input pin, specifically
the Group 1, bit 1 data signal.
Figure 4–1. Case 1: D1 Data Pattern (Ch1) and D1 Latch Clock (Ch2)
LVTTL
Data
Input
LVTTL
Latch-Clock
Input