Datasheet

Receiver Cards
7–339 GTLP EVM Board Typical Test and Setup Configuration
Figure 2–22 shows a monitored receiver card. Monitor points on the right side
are for GTLP Groups 1, 2, 3, 4, 5, and 6. Monitor points on the top are for LVTTL
latch clock, Groups 6, 5, 4, 3, 2, and 1. The LVTTL latch-clock source is either
the system clock or source-synchronous clock. The source-synchronous
clock is the system clock sent via the SN74GTLP1394 driver card along the
1-bit clock trace on the backplane to the SN74GTLP1394 receiver card that
converts it back to LVTTL logic levels.
The monitored receiver card has SMB jacks to monitor selected signals:
- TP1 GTLP level Group 1, bit 1
- TP2 GTLP level Group 2, bit 1
- TP3 GTLP level Group 3, bit 1
- TP4 GTLP level Group 4, bit 1
- TP5 GTLP level Group 5, bit 1
- TP6 GTLP level Group 6, bit 1
- TP7 LVTTL level Group 1, bit 1
- TP8 LVTTL level Group 2, bit 1
- TP9 LVTTL level Group 3, bit 1
- TP10 LVTTL level Group 4, bit 1
- TP11 LVTTL level Group 5, bit 1
- TP12 LVTTL level Group 6, bit 1
- TP13 LVTTL level GTLP latch clock