Datasheet

Driver Cards
7–337 GTLP EVM Board Typical Test and Setup Configuration
2.11.3 Source-Synchronous Clock/System-Clock Selection
Backplanes usually have a system-wide synchronous clock. A system clock
provides an absolute reference time signal from the clock card to every
daughter card at exactly the same time. Source-synchronous clock operation
is different because it allows the absolute system clock to be sent by the
backplane driver along with the data. In the EVM, this is implemented with the
SN74GTLP1394 transceiver on all daughter cards. This transceiver acts as
the driver on the driver cards and as the receiver on the receiver cards. The
SN74GTLP1394 has ERC that is set to the fast edge rate in conjunction with
the JB3 selection.
Source-synchronous clock operation provides a relative clock to all receiver
cards, which removes the flight-time delay restrictions required when an
absolute system clock is used. The flight-time delay depends primarily on bus
length and bus loading.
The driver card uses JB2 to select the transfer mode of operation and to drive
the MODESEL line. Source-synchronous clock operation is selected when the
JB2 jumper shorts the pins, and system-clock operation is selected when the
pins are open (see Figure 2–21). When JB2 is shorted, the SN74GTLP1394
drives the GTLP clock line with a phased system clock. When JB2 is open,
there is no activity on the GTLP clock line. The following options are available:
- JB2 shorted Source-synchronous clock transfer
- JB2 open System-clock transfer
Figure 2–21. JB2 Set to Source-Synchronous Clock (Left) or System-Clock (Right)
Operation