Datasheet

Driver Cards
7–334
The driver daughter card (see Figure 2–18) has SMB monitor points for
selected LVTTL and GTLP signals, in addition to jumpers for Group 1, bit 1
switching (JB1), system or SN74GTLP1394 source-synchronous clock
selection (JB2), and selection of the SN74GTLPH1655 slow or fast edge rate
(JB3). The monitor points along the top edge are the latch clock and the master
data pattern sent to all SN74GTLPH1655 LVTTL A-port inputs. There are no
LVTTL group-bit monitor points because the card always is driven. Monitor
points along the right edge are GTLP Group 1, 2, 3, 4, 5, and 6. The following
signals are monitored:
- TP1 GTLP level Group 1, bit 1
- TP2 GTLP level Group 2, bit 1
- TP3 GTLP level Group 3, bit 1
- TP4 GTLP level Group 4, bit 1
- TP5 GTLP level Group 5, bit 1
- TP6 GTLP level Group 6, bit 1
- TP7 LVTTL level Group 1, bit 1, and master data pattern
- TP8 LVTTL level GTLP latch clock
Figure 2–18. GTLP EVM Driver Daughter Card
JB1
JB2
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
GTLPH1655
GTLP1394
JB2