Datasheet

Backplane Board
7–318
A logic selection line (MODESEL) connects P1-1 through P1-20. The driver
card uses this line to select between source-synchronous and system-clock
operation. The demonstration board is an eight-layer board with separate V
CC
and ground planes. The backplane board stackup is shown in Table 2–2.
Embedded microstrip nominal line width is 0.006 in., dielectric material is
Nelco N4000-13 with a dielectric constant (50% resin contents) of
3.80 @ 100 MHz.
Table 2–2. GTLP EVM Backplane Eight-Layer Stackup
Trace Name Use Layer
Copper
Weight
(oz)
Physical
Representation
Dielectric
Height
(in.)
Dielectric
Name
Top Regulator power/
bypass capacitor/
termination
1 0.5
0.004 B stage
Internal signal 2 Clock distribution/
signal
2 1
0.004 Core
Ground plane Ground plane 3 1
0.004 B stage
Internal signal 3 Data signal 4 1
0.058 Core
Internal signal 4 Data signal 5 1
0.004 B stage
V
CC
V
CC
6 1
0.004 Core
Internal signal 5 Data signal 7 1
0.004 B stage
Bottom Termination 8 0.5