Datasheet

Backplane Board
7–317
GTLP EVM Board Typical Test and Setup Configuration
Figure 2–4. GTLP EVM Backplane Block Diagram
Backplane Overview
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 11
Slot 12
Slot 13
Slot 14
Slot 15
Slot 16
Slot 17
Slot 18
Slot 19
Slot 20
X X
Clock Generator
X = Termination Card on Back of Connector
Table 2–1. GTLP EVM Group Assignment
Group 6 Group 5 Group 4 Group 3 Group 2 Group 1
2 slots 4 slots 8 slots 12 slots 16 slots 20 slots
P1-1 to P1-2 P1-1 to P1-4 P1-1 to P1-8 P1-1 to P1-12 P1-1 to P1-16 P1-1 to P1-20
A single GTLP clock line that runs from P1-1 to P1-20 is used in the
source-synchronous transfer mode.
The GTLP clock and the data lines from groups 2 through 6 have fixed,
on-board, 25- termination resistors. Group 1 data lines terminate on plug-in
cards on the back of the backplane board at P1-1B and P1-20B. This provides
a way to vary the termination resistance or demonstrate other termination
techniques.
The design also uses a system clock that is generated on the clock-driver
board plugged into P3. This system clock is distributed to all 20 slots
simultaneously and is used as the system master timing in the system-clock
mode. Using a separate card for clock generation and distribution is not an
industry standard, but it provides flexibility in using this demonstration board.