Datasheet

SCEA017
7–289 GTLP in BTL Applications
Table 2. High-Drive GTLP Functions
DEVICE AVAILABILITY FUNCTION PINS PACKAGE
SN74GTLP1394 Now
2-bit bus transceiver with split LVTTL port
and feedback path
16 SOIC, TSSOP, and TVSOP
SN74GTLPH1612 Soon 18-bit universal bus transceiver 64 TSSOP
SN74GTLPH1616 Soon
17-bit universal bus transceiver
with buffered clock
64 TSSOP
SN74GTLPH1645 Soon 16-bit bus transceiver 56 TSSOP, TVSOP, and VFBGA
SN74GTLPH1655 Soon 16-bit bus transceiver 64 TSSOP
SN74GTLP1395 Soon
2-bit bus transceiver with split LVTTL port
and feedback path
20
SOIC, TSSOP, TVSOP, and
VFBGA
SN74GTLP21395 Soon
2-bit bus transceiver with split LVTTL port
and feedback path
20
SOIC, TSSOP, TVSOP, and
VFBGA
SN74GTLP2033 Soon
8-bit inverted registered bus transceiver
with split LVTTL port and feedback path
48 TSSOP, TVSOP, and VFBGA
SN74GTLP22033 Soon
8-bit inverted registered bus transceiver
with split LVTTL port and feedback path
48 TSSOP, TVSOP, and VFBGA
SN74GTLP2034 Soon
8-bit registered bus transceiver
with split LVTTL port and feedback path
48 TSSOP, TVSOP, and VFBGA
SN74GTLP22034 Soon
8-bit registered bus transceiver
with split LVTTL port and feedback path
48 TSSOP, TVSOP, and VFBGA
SN74GTLPH1627 Soon
18-bit bus transceiver
with synchronous clock outputs
64 TSSOP
Table 3. FB+ Functions
DEVICE FUNCTION PINS PACKAGE
SN74FB1650 18-bit universal storage transceiver with split TTL I/O 100 PCA
SN74FB1651 17-bit universal storage transceiver with delayed buffered clock with split TTL I/O 100 PCA
SN74FB1653
17-bit universal storage transceiver with delayed buffered clock
with split LVTTL I/O (3.3-V and 5-V V
CC
)
100 PCA
SN74FB2031 9-bit address/data transceiver with clock and latch 52 RC
SN74FB2032 9-bit arbitration contest competition transceiver 52 RC
SN74FB2033A 8-bit registered transceiver with split TTL I/O 52 RC
SN74FB2033K 8-bit registered transceiver with split TTL I/O 52 RC
SN74FB2040 8-bit status/sync transceiver with split TTL I/O 52 RC
SN74FB2041A 7-bit transceiver with split TTL I/O 52 RC