Datasheet

SCEA017
7–287 GTLP in BTL Applications
• Differential input – FB+ devices have a fixed differential input set at 1.55 V, whereas GTLP
devices have a variable differential input that is set via the external V
REF
control pin.
Normally, V
REF
is two-thirds of V
TT
so that, when V
TT
is 1.5 V, V
REF
is 1.0 V. As shown in
Figure 5, the GTLP reference level is set by this simple R/2R resistor network, with R
typically being a one-fourth-watt resistor in the range of 1 kΩ ± 1%. The advantage of this
external V
REF
and R/2R network is that it maintains the upper and lower noise margin if V
TT
fluctuates. The maximum input V
REF
current to a GTLP device is 10 mA. A 0.1-mF to 0.01-mF
bypass capacitor should be located as close to the V
REF
pin as possible to stabilize the
voltage.
When GTLP is used in BTL applications, the resistor network simply is changed to R/3R so
that V
REF
is set at 1.575 V when V
TT
is changed to 2.1 V. When the card is converted from
BTL to GTLP signal levels, simply change the 3R resistor to 2R, and the proper reference
voltage is set when V
TT
is reduced from 2.1 V to 1.5 V.
V
REF
V
TT
C
R
2R
Figure 5. GTLP V
REF
Resistor Network
• Transistor type – FB+ and GTLP operate the same using only a pulldown transistor on the
output, with FB+ bipolar transistors being called open collector and GTLP CMOS transistors
being called open drain.
• Drive levels – The drive or current-sinking capability is the same and is 100 mA, to allow
termination-resistor R
TT
values down to 22 Ω (effective termination resistance of 11 Ω) if the
voltage swing is limited to 1 V. In actual applications, the GTLP V
OL
is lower, and higher R
TT
values are required to avoid exceeding the recommended I
OL
.
• Input/output capacitance (C
io
maximum) – The FB+ decoupling diode reduces the maximum
output capacitance to about 6 pF. Increased output capacitance of 10.5 pF (8.5 pF typical) is
seen in GTLP devices, compared to FB+ devices. This is directly attributable to the GTLP
CMOS process, which requires larger-area output structures compared to bipolar output
structures used on FB+ devices. This increase in capacitance reduces the loaded-bus line
impedance that can be compensated for by lowering R
TT
. The higher loading reduces t
pd
and
increases the time of flight.
• Live insertion – Both support live insertion through the use of I
off
, PU3S, and BIAS V
CC
circuitry. BIAS V
CC
circuitry precharges the outputs to mid-swing levels to prevent glitching
active data on the backplane when cards are inserted or removed, and is disabled when V
CC
is connected. FB+ BIAS V
CC
output is fixed at 1.62 V to 2.1 V, whereas the GTLP device
BIAS V
CC
output is fixed at 0.95 V to 1.05 V. If GTLP devices are used at BTL signal levels,
the precharge is below the threshold level and may not be as effective in preventing data
glitches. However, in the GTLP EVM (a specially designed backplane for customer use), no
glitching was noted when GTLP devices were operated at BTL levels.