Datasheet
SCEA017
7–284
GTLP in BTL Applications
The GTLP family combines the high-drive benefits of the BTL family, with the reduced power
consumption of the GTL family. GTLP specifically is designed and optimized for heavily loaded
multipoint backplane applications with a slow, controlled, backplane edge rate, and includes
features needed for live insertion and withdrawal.
GTL and GTLP devices support two different signal-level specifications: GTL (JEDEC Standard
JESD 8-3) and GTL+ signal levels first used by Intel in their Pentium processors. GTL
voltage swing is from 0.4 V to 1.2 V, with the threshold in the middle of the voltage swing at
0.8 V. GTL+ voltage swing is from 0.55 V to 1.5 V, with the threshold at 1.0 V. GTLP devices,
which are optimized for backplane applications and are designated with the SN74GTLP prefix,
are optimized for the higher noise-margin GTL+ signal levels to indicate they have a slower slew
rate with improved output-edge control, and to differentiate them from point-to-point
GTL+-optimized devices.
Both FB+ and GTLP devices are commonly used in multiple-bit, multipoint double-terminated
parallel backplanes (see Figure 3). The device turns on to pull the signal low and turns off to
allow the termination resistors to pull the signal high, up to the termination voltage. The benefit
of this open-collector/open-drain technology is that the output either is sinking current or is in the
high-impedance state (3-state), but never sources current. This reduces the power consumption
over typical Thevenin or ac terminations. Other benefits include the ability to pick a
termination-resistor value that matches the loaded backplane impedance (Z), ensuring
incident-wave switching/optimum signal integrity, and no destructive bus-contention issues if
multiple devices are on at the same time, which also facilitates a wired-OR arrangement. The
loaded backplane impedance, Z, always is lower than the natural bus line impedance (Z
o
) and
varies from system to system, depending on stub length, slot pitch, device C
io
, and type of
connectors. Surface-mount ceramic-bypass capacitors (0.82 nF) should be connected between
V
TT
and GND on every fourth data bit, to minimize current fluctuations.
1.5 V
Drvr
1.5 V
.25” 1”
1” 1”
1”1”
1” .25”
22 Ω
Rcvr
Rcvr
Rcvr
Slot 1 Slot 2 Slot 19 Slot 20
Conn.
Conn. Conn. Conn.
Z
o
= 50 Ω
22 Ω
Figure 3. Typical Backplane Physical Representation