Datasheet

SCEA022
7–279
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
6 Glossary
BTL Backplane transceiver logic
CMOS Complementary symmetry metal-oxide semiconductor
CSSC Central-synchronous system clock
DUT Device under test
FB FutureBus (device identifier for backplane transceiver logic devices)
GND Ground
GTLP Gunning transceiver logic plus
I/O Input/output
LVTTL Low-voltage transistor-transistor logic with 3.3-V supply, compatible with TTL
PCB Printed circuit board
Slew rate Slew rate, which is derived using the following equation:
slew rate = ∆V/∆t = (0.8 V
OH
– V
OL
)/t
r,f
SSSC Source-synchronous system clock
TTL Transistor-transistor logic
t
pd
Propagation delay time
t
f
Time to transit from logical high to logical low,
measured between the 90% and 10% values of the steady logical-high level
t
r
Time to transit from logical low to logical high,
measured between the 10% and 90% values of the steady logical-high level
Transceiver Trans(mitter) (re)ceiver, bidirectional device
V
CC
Supply voltage