Datasheet

SCEA022
7–278
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
5 Summary
With the central-clock-distribution system, the highest possible system pulse rate is about
50 MHz (assuming a 19-inch backplane). With the source-synchronous system, the clock
frequency can be increased by a factor of 2.4, to 120 MHz.
Table 2 lists three system solutions, along with relevant parameters that must be taken into
account during system design.
Table 2. Comparison of Parallel Bus Systems With Different Pulse Supplies
SYNCHRONOUS SYSTEM ASYNCHRONOUS SYSTEM
PARAMETER
CENTRAL-CLOCK
DISTRIBUTION
SOURCE-SYNCHRONOUS
CLOCK DISTRIBUTION
NO SYSTEM CLOCK PULSE
Pulse skew
Output-to-output
pulse driver
(to be taken into account)
Output-to-output
pulse driver
(to be taken into account)
Not applicable
t
pd
CLKAB
Device dependent
(to be taken into account)
Device dependent
(to be taken into account)
Not applicable
∆ Data – pulse –/– To be fixed Not applicable
t
pd
(sim.switch)
Package dependent
(to be taken into account)
Package dependent
(to be taken into account)
Package dependent
(to be taken into account)
t
sk(o)
Device dependent
(to be taken into account)
Device dependent
(to be taken into account)
Device dependent
(to be taken into account)
Bus propagation delay time
Bus dependent
(to be taken into account)
0 ns
Not applicable
Bus dependent
(to be taken into account)
Setup time
Package dependent
(to be taken into account)
0 ns
Not applicable
Not applicable
For the central-system-clock solution, a central clock exists for all bus attendees. The maximum
clock speed is about 50 MHz and provides a 32-bit data width and a data throughput rate of up
to 1.6 Gbit/s. A significant limiting factor for the time budget is the transit time via the bus.
For a system with a source-synchronous system clock, the clock signal, with a slight shift in time
to the data, is sent together with the data signal on the bus. The delay between data and clock is
constant for all bus members. The maximum clock speed is about 120 MHz. The 32-bit data
width results in 3.8 Gbit/s as the maximum data throughput. A significant limiting factor for the
time budget in this setup is the propagation time, compared with the clock period.
A further option is asynchronous data transfer, in which an integrated system clock does not
exist. All the bus drivers are in transparent mode, and switch the outputs according to their
propagation time. Therefore, there is no common clock speed.
The asynchronous data frequencies can be 160 MHz, or more, depending on the technology.
However, the effective maximum frequency is reduced significantly by additional requirements,
such as the introduction of a bus protocol, which is indispensable in this system. The maximum
frequencies that produce the theoretical data rate, which is based on 32 bits of up to 5.12 Gbit/s
(at160 MHz), can be reached only for a short time, not continuously.