Datasheet

SCEA022
7–277
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 225 ns 250 ns 275 ns 300 ns
Propagation Time, 25 ns/Div
FULLY LOADED BACKPLANE AT 66 MHz, R
TT
= 38 Ω, ERC = V
CC
Volts, 0.5 V/Div
GTLP Bus Begin GTLP Bus End Receiver Clock Receiver Out LVTTL
Figure 21. Fully Loaded Backplane, SSSC, Transmitter in Slot 1, Receiver in Slot 20
Even if the bus is fully loaded, a correct signal transfer can be observed. The only drawback is
the need for an additional line in the bus layout. The clock signal always is transferred, with a
small delay, to the present datum. The increase in propagation delay time via the bus, as a
result of the additional input capacitance of the inserted modules, no longer is relevant.
The maximum frequency is calculated using data-sheet values, realistic approximations, and
equation 2:
f
max
(
CLK
)

1
0.5 ns  5.8 ns  1.0  1ns

1
8.3 ns
 120.4 MHz
(6)