Datasheet

SCEA022
7–276
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
4.2 Data Transfer With Source-Synchronous Clock
The sender is switched to source-synchronous clock mode by moving a jumper on the driver
card. Comparing the signals on the empty backplane, there is little difference, as similar results
are seen in the oscilloscope pictures (see Figure 16).
In the source-synchronous mode, the signal is within the same clock period (see Figure 20). The
clock pulse no longer has any relation to the signal on the bus, because the clock pulse is
measured at the receiver and, therefore, has a proper relation only to the TTL output signal.
0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 225 ns 250 ns 275 ns 300 ns
Propagation Time, 25 ns/Div
EMPTY BACKPLANE AT 66 MHz, R
TT
= 38 , ERC = V
CC
Volts, 0.5 V/Div
GTLP Bus Begin GTLP Bus End Receiver Clock Receiver Out LVTTL
Figure 20. Signals on Empty Backplane, SSSC, Transmitter in Slot 1, Receiver in Slot 20