Datasheet

SCEA022

7–275

Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)

Therefore, the required period in this case is 21 ns, increasing the chosen clock period from

66 MHz by 6 ns. The consequence is that not all modules receive the same data with the same

clock edge. Some modules receive the data with the active edge of consecutive clock periods,

as shown in Figure 19. With an empty backplane (see Figure 18), the data was transmitted with

the next active edge of the clock signal at the receiver output. In this case, it takes one more

clock period (see Figure 19).

In other words, the system no longer is working synchronously, and errors due to missing

synchronicity can result.

0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 225 ns 250 ns 275 ns 300 ns

Propagation Time, 25 ns/Div

FULLY LOADED BACKPLANE AT 66 MHz, R

= 38 Ω, ERC = V

Volts, 0.5 V/Div

GTLP Bus Begin GTLP Bus End Receiver Clock Receiver Out LVTTL

Figure 19. Empty Backplane Transmitter, CSSC in Slot 1, Receiver in Slot 20