Datasheet

SCEA022
7–274
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
The EVM is used to illustrate the difference between system-synchronous data transfer and
source-synchronous data transfer. The transmitter is at the beginning of the bus line, and the
receiver is at the end of the bus. In both cases, 66 MHz is the clock speed, and gives a clock
period of 15.15 ns.
4.1 Data Transfer With System-Synchronous Clock
The propagation time of the signal via the bus amounts to about 4 ns, if all other slots are empty.
If the characteristics of the interface modules using GTLPH1655 devices are included, the
worst-case scenario for the maximum clock speed is:
f
max
(
clk
)

1
0.5 ns  5.8 ns  1.1 ns  1ns 4ns 2.6 ns

1
15 ns
 66.7 MHz
With no load on the bus, timing already is critical at 66-MHz clock frequency because the timing
margin is only 150 ps.
However, GTLPH1655 devices typically have less propagation time (about 3.5 ns compared with
data-sheet value of 5.8 ns), thus, the critical frequency increases to about 78.7 Hz (see
Figure 18).
0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 225 ns 250 ns 275 ns 300 ns
Propagation Time, 25 ns/Div
EMPTY BACKPLANE AT 66 MHz, R
TT
= 38 Ω, ERC = V
CC
Volts, 0.5 V/Div
GTLP Bus Begin GTLP Bus End Receiver Clock Receiver Out LVTTL
Figure 18. Empty Backplane Transmitter, CSSC in Slot 1, Receiver in Slot 20
However, if additional modules are inserted into the backplane, the capacitive load and, thus, the
propagation delay time via the bus, increases significantly. In this case, the propagation delay
time via the bus increases to about 10 ns. As a result, the maximum clock speed is significantly
lower:
f
max
(
clk
)

1
0.5 ns  5.8 ns  1.1 ns  1ns 10 ns  2.6 ns

1
21 ns
 47.6 MHz
(4)
(5)