Datasheet

SCEA022
7–273
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
TP8 TP7
LVTTL Monitor Points
TP1
TP2
TP3
TP4
TP5
TP6
JB1
No. 1 Bit
Not Switch Selection
JB3
Slow/Fast Edge-Rate Selection
A Port = LVTTL Data I/O
B Port = GTLP Data I/O
GTLPH1655
GTLP1394
V
ref
Resistors and
Bypass Capacitor
AMP Through-Hole Connector
JB2
Source-Synchronous
Clock Selection
Figure 16. Layout of Driver Card With Monitor Points and Jumpers
Figure 17 shows a receiver card. The receiver card contains GTLPH1655 transceivers that
receive data from the GTLP bus and translate it into LVTTL signals.
TP1
TP2
TP3
TP4
TP5
TP6
TP13
TP12
TP11
TP10
TP9
TP8
TP7
TTL-Level Signals (Module Side)
GTLP-Level Signals
(Bus Side)
Source-Synchronous Clock
Figure 17. Receiver Card With Monitor Points
Using the receiver card, GTLP bus measurements (GTLP level) and module measurements
(LVTTL level) are possible.