Datasheet

SCEA022
7–270
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
t
sk(clk)
Clock Skew
Sender Active Edge (CLK)
Received Clocking
in Data (D
1
)
Period = 1/f
clock
Sender Active Edge (CLK)
Transmitted
Timing
Margin
t
pd
max
From CLK to B
t∆
OUT
t
setup
t(rec)
t
hold
Flight-Time Clock
Propagation Delay
Over Bus Line
t(sender)
D
1
D
2
D
n
D
n+1
Sender In
D
1
D
n–1
D
n
Sender Out
Don’t Care
Sender Clocks in D
1
Sender
Clocks
in D
2
Sender Sets D
1
Sender Sets Clock (D
1
)
Data (D
1
)
Reaches Receiver
Receiver Clocks in D
1
Sender Active Edge (CLK)
Received Clocking
in Data (D
2
)
Receiver Active Edge (CLK)
Received Clocking
in Data (D
1
)
Flight-Time Data
Figure 13. Time Budget for Source-Synchronous Clock Distribution
In this case, error-free synchronous data transfer that is independent of the propagation delay
time over the line is possible (see Figure 14). The clock signal – with certain propagation to the
data signal – is transferred via a separate clock line.