Datasheet

SCEA022
7–269
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
3.3 Source-Synchronous Clock Distribution
To eliminate the signal propagation delay time on the bus, the solution illustrated in Figure 12
can be used. An additional line for the source-synchronous clock signal and other lines for the
arbitration or transmission of the send/receive status are required. However, propagation delay
time over the bus (t
flight)
is eliminated from the calculation of the maximum clock frequency.
Therefore, a significantly higher system speed is possible.
Module 1
16 . . . 128
R
TT
= 22 Ω
V
TT
R
TT
= 22 Ω
V
TT
Module X
16 . . . 128
Number of modules can
vary, depending on the bus
length, e.g., on a 19-inch
backplane, 20 modules can
be plugged in.
16 . . . 128
Data bus could be 16 to 128 bits.
Z
o
can decrease to 25 Ω,
depending on number of modules and layout.
From Main System Clock From Main System Clock
V
TT
V
TT
R
TT
= 22 Ω R
TT
= 22 Ω
Source-Synchronous Clock Line
Figure 12. Principle of Source-Synchronous Clock Distribution
The times to be observed refer to two successive clock periods. The first clock period includes
times that must be taken into account relative to the transmitter, while the second clock period
includes critical times for the receiver. There are two requirements for the maximum clock
speed:
f
max
(clk) 
1
t
sk
(
clk
)
 t
pd
(
clk to B
)
 t
sk(o)
 Dt
pd
(
sim.sw.transm.
)
f
max
(clk) 
1
t
hold
(
rec
)
 t
setup
(
rec
)
The smaller value for f
max
from equations 2 and 3 represents the highest possible frequency.
Figure 13 shows this correlation graphically.
(2)
(3)