Datasheet
SCEA022
7–268
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
t
clk
Clock
System
Synchronous
t
pd
Sender
Data
Out
D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18
Case 1: Bus Delay Matches Timing for Central System-Clock Data Transfer
D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18
Data at
Receiver
t
su
t
bus
delay
Receiver
Reads
<
Case 2: Bus Delay Exeeds One Clock Cycle
D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18
t
bus
delay
Data at
Receiver
D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
Lost Cycle
Receiver
Reads
=
Figure 11. Two Examples for Data Transmission in a Central Synchronous
System Clock Distribution Environment
The maximum frequency is calculated from the skew of the clock-distribution circuit [t
sk
(clk)], the
device propagation (t
pd
), the skew of the driving device, the additional propagation delay time
(∆t
pd
) due to simultaneous switching of several outputs, the transit time via the bus [t
flight
(bus)],
as well as the setup time of the connected receiver [t
setup
(rec)]. The formula for calculating the
maximum frequency is:
f
max
(
clk
)
1
t
sk
(
clk
)
t
pd
(
clk to B
)
Dt
pd
(
sim.sw.transm.
)
t
sk(o)
t
flight
(
bus
)
t
setup
(rec)
With:
t
sk(o)
(clk) = 0.5 ns
t
pd
(GTLPH1655) = 5.8 ns
∆t
pd
= 1 ns
t
sk(o)
= ns
Transit time via the bus t
flight
(bus) = 10 ns
Setup time for the receiver t
setup
(rec) = 2.6 ns
f
max
= 47.8 MHz
Central-synchronous clock distribution propagation delay time via the bus takes a large part of
the available clock period. The propagation delay over the bus can be lower if the capacitive
load is lower. For example, if only the transmitter and one receiver card are plugged into the bus
and no additional modules are inserted, the maximum f
max
(clk) must be put in the formula for a
safe circuit design, i.e., assume that all slots are filled with cards.
(1)