Datasheet

SCEA022
7–267
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
CLK (0)
Active Edge
CLK (1)
Active Edge
Time Budget
∆t
pd
Simultaneous Switching
+ t
sk(o)
t
pd
max From CLK to B Flight Time
Timing
Margin
Propagation
Delay
Over Bus Line
For Safe
Design,
e.g.,
to Handle
Tolerances,
etc.
t
su
Setup Time
Sender Clocks Data Out
Data Reaches Receiver
Receiver Clocks in DataSender Clocks in Data
Period = 1/f
clock
t
sk(clk)
Clock Skew
Data Position
Within One Clock Period
NOTE: No additional clock signal line is required because all receivers refer to system clock.
Figure 10. Time Budget for Central Synchronous System Clock Distribution Environment
The need for all system parts to receive the clock at the same time is a disadvantage because
the propagation delay time of the data signals via the bus must be taken into account when
determining the maximum frequency of the system.
The transmitted data must propagate over the distance from the transmitter to the receiver
within a single clock cycle, because the transmitter and the receiver work with exactly the same
active edge of the clock signal.
Should the data fail to reach the receiver input within a clock period, the synchronicity of the
system no longer can be ensured. In this case, the signal reaches one part of the bus system at
the right time (within the same clock period), while another part does not receive the signal until
one clock period later. This effect is shown as case 2 of Figure 11.