Datasheet

SCEA022
7–266
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
3.2 Central Synchronous Clock Distribution
A basic prerequisite for a synchronous system is that the transferred signals refer to a common
clock signal that is transmitted from a central clock distribution circuit. In the layout shown in
Figure 9, the active clock edge reaches all parts of the system as simultaneously as possible.
For skew adjustment, the line lengths have been chosen to be as close as possible.
Module 1
16 . . . 128
R
TT
= 22 Ω
V
TT
R
TT
= 22 Ω
V
TT
Module X
16 . . . 128
Number of modules can
vary, depending on the bus
length, e.g., on a 19-inch
backplane, 20 modules can
be plugged in.
16 . . . 128
Data bus could be 16 to 128 bits.
Z
o
can decrease to 25 Ω, depending on number of modules and layout.
Clock Driver
For the lowest skew, make all
interconnecting clock lines the same length.
Figure 9. Principle of Central Synchronous Clock Distribution
Figure 10 shows the time budget for the central-clock distribution. All times that must be taken
into account are shown. The main contributors of time in the timing budget are the propagation
delay time of the device and the propagation delay time over the bus.