Datasheet

SCEA022
7–265
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
3.1.3 Setup and Hold Times at Receiver Input
In a synchronous system, a common clock signal, which is synchronous for all the interface
devices (e.g., registers or flip-flops) exists. Figure 8 shows the definitions for setup and hold time
based on a D flip-flop. Both times are defined around the active edge of the clock signal.
Data
t
su
t
h
t
d
Clock
Output
t
pd
t
pd
Critical Time Window
t
d
= 10 . . . 150 ps
Metastable
Output
V
IH
V
IL
Possible
Malfunction
Q
Q
CLK
QD
Clocked D-Type Flip-Flop
NOTE: The setup and hold times are given in the data sheets. For GTLPH1655, t
su
is 2.6 ns and t
h
is 0.5 ns.
Figure 8. Setup and Hold Times
The setup time is the time during which a data signal must be stable before the active edge of
the clock input occurs. The hold time is the time during which a data signal must be stable after
the active edge of the clock input occurs. Should either of the two times be violated, it is possible
that the output can be in a metastable state in the critical time window. The result can be a state
in undefined range or even in the threshold region, that represents neither a logical 1 nor a
logical 0. The consequence can be that the subsequent stage can interpret the value as either
high or low. Therefore, the probability of malfunctions increases dramatically.