Datasheet

SCEA022
7–260
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
While the inductive layer remains almost constant in all three cases, the connectors, stub lines
to the connector, and driver input and output, as well as the input capacity of the receiver,
represent an additional capacitive load for the line. The increased capacitive load reduces the
line impedance and starts the demand for higher driver capability for bus-interface logic.
However, the signal propagation delay time via the bus increases significantly (by a factor of
more than three in the example above)
Changing the distances between the modules affects the capacitive layer of the line as shown in
Figure 3.
†
Assuming a capacitive load of 2 pF per slot (connector only)
‡
Assuming a capacitive load of 10 pF per slot (complete module)
100
90
80
70
60
50
40
30
20
10
0
2 cm 3 cm 4 cm 5 cm 6 cm
2 inches1 inch
Slot Spacing
Line Impedance –Ω
Limit GTLP Medium-Drive Option
Limit GTLP Heavy-Drive Option
Line-Impedance Backplane
Open-State Bus
†
Fully Loaded Bus
‡
Figure 3. Effect of Slot Spacing on Line Impedance