Datasheet

SCEA022
7–259
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
R
1
R
2
V
TT
d = 1 inch
V
TT
R
1
R
2
C
0
C
L
L
0
R
TT
C
0
C
L
L
0
L
0
L
0
C
0
C
L
R
TT
Figure 2. Additional Capacitive Load of Line by Modules
If the distances between the inserted modules remain electrically short, i.e., twice the
propagation delay time between two inserted modules is shorter than the rise/fall time of the
signal, it is possible to add the capacitive load to the capacitive layer. The influence on the
inductive layer is negligible.
Table 1 shows the comparison between a point-to-point connection on a PCB, an unloaded bus
line with the bus connectors only, and a fully loaded bus. The distance between the slots is
1 inch.
Table 1. Comparison of PCB Line and Bus Line (Slot Distance = 1 Inch)
LINE PARAMETER
OPEN LINE
LOADED LINE
LINE
PARAMETER
PCB BUS
(BUS)
Inductive layer, L
0
6.5 nH/cm 6.5 nH/cm 6.5 nH/cm
Capacitive layer, C
0
0.4 pF/cm 0.4 pF/cm 0.4 pF/cm
Connector Not applicable 2 pF per slide-in module 2 pF per slide-in module
Feed line to backplane side of connector Not applicable <<1 pF <<1 pF
Feed line to module side of connector Not applicable Not applicable ~1 pF
Input capacity of receiver Not applicable Not applicable 9 pF
Additional capacity load, C
L
Not applicable 2 pF/2.54 cm 10 pF/2.54 cm
Capacitive load per cm 0.4 pF 1.2 pF 4.73 pF
Line impedance, Z
o
127 Ω 74 Ω 37 Ω
Propagation delay time of signal, τ 5.1 ns/m 8.8 ns/m 17.5 ns/m