Datasheet

7–215
This flexible design approach eliminates the need for double-sided surface mounting, along with all of the associated
manufacturing costs, and still meets the IEEE 896.2-1991 25-mm maximum-stub-length requirement (see Figure 7).
TFB2002
I/O Controller
TFB2022
64-Bit
Data-Path
Unit
TFB2010
Arbitrator
FB16xx FB2032
25-mm Maximum Stub Length
Address/Data Status Command Arbitration Sync
Connector
FB16xx FB16xx FB16xx FB16xx FB16xx
NOTE: There is no double-sided SMT requirement.
Figure 7. Uncached 64-Bit Futurebus Layout With Texas Instruments Chipset
and FB16xx Transceivers
In addition, the 18-channel architecture lends itself naturally to reduced pin-to-pin signal skew. Advanced BiCMOS circuit design
techniques have improved propagation-delay performance over the previous generation of BiCMOS transceivers. Table 3 shows
a transceiver description for the same 64-bit uncached Futurebus example considered previously (see Table 2).
Table 3. Transceiver Descriptions for 64-Bit Uncached Futurebus Board
Using FB16xx Series Transceivers
DEVICE DESCRIPTION
QUANTITY
PER
BOARD
FB16xx 18-Bit TTL/BTL UBT With Split TTL I/O 6
FB2032
†
Arbitration Contest Transceiver 1
Total Part Count 7
†
Optional for distributed arbitration only
This is nearly a 50% reduction in component count and approximately 15% in cost savings on the transceivers alone. Significant
savings (tens of dollars per board) in manufacturing costs also are realized by moving to single-sided SMT manufacturing. Other
members of the FB16xx family include system clock-distribution features that lend themselves to more specific end-system
applications such as ATM hubs and routers (see Table 4).
Table 4. Transceiver Descriptions for Other Members of the FB16xx Series
DEVICE DESCRIPTION
FB1650 18-Bit TTL/BTL UBT With Split TTL I/O
FB1651 17-Channel UBT With Separate Buffered and Delayed Clock Bit
FB1653 17-Channel UBT With Separate Buffered Clock Bit (variable delay lines)