Datasheet

7–201
Signal Integrity
Figures 15 and 16 show the signal integrity of data propagating across the 50-Ω transmission line using three cable lengths
(A = 12 in., B = 28 in., and C = 46 in.). The clock frequency is 75 MHz. The measurement was taken at the receiver end of the
cable. The GTL output waveform has kept its input square-wave shape better than the BTL waveform has. The cable and the
termination resistors used in this laboratory are not precisely matched; that is why a small reflection can be seen on the GTL
outputs when switching low to high. In real systems, where both the termination resistor and the traces are matched, these
reflections will be reduced.
C
GND
A
FB1650
Channel 1 = 500 mV/div, Timebase = 5 ns/div
Distance between driver and receiver:
A = 12 in., B = 28 in., C = 46 in.
T
A
= 25°C, V
CC
= 5 V, V
IH
= 3 V, V
IL
= 0 V, BIAS V
CC
= 5 V, BG V
CC
= 5 V, V
TT
= 2.1 V, R
TT
= 33 Ω, Frequency = 75 MHz
2.1 V
B
Figure 15. FB1650 Signal Integrity at the Receiver Input Using Different-Length Cables
A
T
A
= 25°C, V
CC(5)
= 5 V, V
CC(3.3)
= 3.3 V, V
IH
= 3 V, V
IL
= 0 V, V
TT
= 1.2 V, R
TT
= 50 Ω, Frequency = 75 MHz
GND
B
GTL16612
Channel 1 = 500 mV/div,
Timebase = 5 ns/div
Distance between driver and receiver:
A = 12 in., B = 28 in., C = 46 in.
2.1 V
C
Figure 16. GTL16612 Signal Integrity at the Receiver Input Using Different-Length Cables
Design Considerations
To successfully design with the GTL family, several rules and techniques with regard to voltage generation and proper termination
must be followed. First, both 3.3-V and 5-V V
CC
are needed in the present generation of GTL devices (only the 3.3-V V
CC
will
be needed in the next-generation GTL). Second, the termination voltage (V
TT
) should be regulated from the 5-V V
CC
, keeping
in mind the current requirements of the outputs (40 mA per output). There are several linear regulators that are capable of
performing this function. Depending on the design, the regulator could be either on the backplane itself or on the individual cards.
Third, the reference voltage (V
REF
) must be generated from V
TT
. The V
REF
voltage can be generated using a simple
voltage-divider circuit with an appropriate bypass capacitor (0.01 µF or 0.1 µF) placed as close as possible to the V
REF
pin. The
V
REF
input circuitry consumes very little power (1 µA maximum). This enables several devices to have their V
REF
pin connected
to the same voltage-divider circuit, thus eliminating the need for multiple voltage-divider circuits (see Figure 17).