Datasheet

7–194
Advantages of GTL or BTL Over CMOS/TTL
BTL and GTL were developed to solve the bus-driving problem associated with TTL and to enhance the performance of
point-to-point and backplane applications. BTL and GTL also eliminate the need for the extra time required for the TTL signal
to settle due to reflection and noise generated when switching. The 1-V swing of both signals versus the 3-V to 5-V swing of TTL
and CMOS signals helps reduce the noise generated on the bus when the outputs are switching simultaneously. Table 1 shows
the minimum high-level output voltage (V
OH
) and the maximum low-level output voltage (V
OL
) of CMOS, TTL, BTL, and
GTL signals.
Table 1. V
OH
and V
OL
Levels for Various Families
LOGIC
LEVEL
V
OH
min
(V)
V
OL
max
(V)
CMOS 3.8 0.44
TTL 2.4 0.55
BTL 2.1 1
GTL 1.2 0.4
GTL+ 1.5 0.4
BTL and GTL buffers are designed with minimal output capacitance (5 pF maximum) compared to a TTL output buffer (8 pF
to 15 pF typical). A TTL or CMOS output capacitance, coupled with the capacitance of the connectors, traces, and vias reduces
the characteristic impedance of the backplane. For high-frequency operation, this phenomenon makes it difficult for the TTL or
CMOS driver to switch the signal on the incident wave. A TTL or CMOS device needs a higher drive current than presently
available to be able to switch the signal under these conditions. However, increasing the output drive clearly increases the output
capacitance. This scenario again reduces the characteristic impedance even more. That is why a lower signal-swing family with
reduced output capacitance, such as BTL or GTL, is recommended when designing high-speed backplanes.
GTL Family Input and Output Structure
The GTL input receiver is a differential comparator with one side connected to the externally provided reference voltage, V
REF
.
The threshold is designed with a precise window for maximum noise immunity (V
IH
= V
REF
+ 50 mV and V
IL
= V
REF
– 50 mV).
The output driver is an open-drain n-channel device which, when turned off, is pulled up to the output supply voltage (V
TT
). When
turned on, the device can sink up to 40 mA of current (I
OL
) at a maximum output voltage (V
OL
) of 0.4 V. The output is designed
for a 50-Ω transmission line terminated at both ends (25-Ω total load). The inputs and outputs are designed to work independently
of the device’s V
CC
. They can communicate with devices designed for 5-V, 3.3-V, or even 2.5-V V
CC
. The TTL input is a 5-V
tolerant 3.3-V CMOS inverter that can interface with 5-V TTL signals. Bus hold is also provided on the TTL port to eliminate
the need for external resistors when the inputs and outputs are unused or floating. The TTL output is a bipolar output. It is similar
to the LVT output structure.
1
At this time, the GTL16612 and GTL16616 devices require two power supplies to function: a 5-V
supply (V
CC(5)
) for the GTL and a 3.3-V supply (V
CC(3.3)
) for the LVTTL. The maximum operating frequency of the family
is 95 MHz (GTL16612 and GTL16616). The GTL16622 and GTL16923 will operate up to 200 MHz in both directions (GTL
to TTL or TTL to GTL) and will have a single 3.3-V power supply.
1
Figure 3 shows a typical GTL input and output circuit.