Datasheet

viii
GTLP FAMILY SUMMARY (CONTINUED)
Additional features of GTLP devices:
• I
off
circuitry prevents damage to the device during partial power down, a feature of
all GTLP devices (see I
off
in the data sheets).
• PU3S forces outputs to the high-impedance state during power up and power
down, which prevents driver conflict during hot swap or hot insertion, a feature of all
GTLP devices (see I
OZPU
and I
OZPD
in the data sheets).
• BIAS V
CC
circuitry allows easy internal precharging of backplane I/O pins for true
live-insertion applications where active backplane data cannot be suspended or
disturbed during circuit-board insertion or removal, a feature of all GTLP devices,
except GTLPH306 and GTLP817 (see BIAS V
CC
in the data sheets).
• Bus hold eliminates floating inputs by holding them at the last valid logic state. This
eliminates the need for external pullup and pulldown resistors on unused or
undriven inputs, reducing power requirements, cost, and board-layout time.
Devices with an H in the device name have the bus-hold feature. There is no
bus-hold circuitry on the B port (GTL/GTL+ side) because this defeats the purpose
of open-drain outputs that take on the high-impedance state, which allows the bus
to achieve a logic-high state via the pullup resistors.
• Improved OEC circuitry controls the rising and falling edges of the GTL/GTL+
outputs (a feature of all GTLP devices) and reduces line reflections and EMI,
thereby, improving overall signal integrity.
• TI-OPC circuitry actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal
transitions, thus, improving signal integrity, which allows adequate noise margin to
be maintained at higher frequencies.
• ERC is a feature of all high-drive GTLP devices and the medium-drive GTLP817.
Fast or slow edge rates are achievable by holding the ERC pin at V
CC
or GND,
respectively.
– The fast edge rate is useful in point-to-point applications and when the backplane has
been optimally terminated.
– The slow edge rate is used in less than optimally terminated backplane applications
where the slow edge reduces overshoot and ringing.
• GTLP devices are available in small-outline integrated circuit (SOIC), shrink
small-outline package (SSOP), thin shrink small-outline package (TSSOP), thin
very small-outline package (TVSOP), low-profile, fine-pitch ball grid array
(LFBGA), and very low-profile, fine-pitch ball grid array (VFBGA) packages to fit
any design requirements.