Datasheet

7–168
Power-Up or Power-Down High Impedance
Power-up 3-state circuitry is another feature that TI offers on selected LVT, ABT, and FB. This feature keeps the output in a
high-impedance state during power up or power down, regardless of the output-enable control pin’s state (V
CC
= 0 V to 2.1 V
for ABT and FB, and V
CC
= 0 V to 1.5 V for LVT). After V
CC
reaches the specified value, the output-enable control takes over
and puts the device in the required state (see Figure 39). The electrical characteristics table in the data sheet has both the
power-up and power-down specifications (I
OZPU
and I
OZPD
). These specifications show the test condition and the maximum
leakage an output can source or sink when V
CC
is between 0 V and 2.1 V for ABT and FB or between 0 V and 1.5 V for LVT
(the nomenclature for the selected LVT devices that offer this feature is LVTZ). Refer to the LVT data book for more details.
Power-up or power-down high impedance can also be achieved with other families by adding an external pullup or pulldown
resistor (typically 1 kΩ) from the output-enable pin to V
CC
(active-low devices) or to GND (active-high devices) (see
Figure 40). This ensures the high-impedance state during the full V
CC
ramp. As long as the output-enable pin is not driven to
an active state by the controlling device, an ASIC, FPGA, or PAL, the output remains disabled.
0
1
2
3
4
5
Output Status
ABT, FB
LVTZ
On
On
OffOff
OffOff
2.1 V
1.5 V
2.1 V
1.5 V
Figure 39. Power-Up and Power-Down High Impedance Up to 2.1 V (ABT, FB) and 1.5 V (LVTZ)
Control Circuit
V
CC
Enable Pin (active low)
I
OL
†
I
R
†
†
I
OL
> I
R
, so the control signal can override the pullup resistor.
ASIC, FPGA, or PAL Device
V
CC
Figure 40. Power-Up High Impedance With Active-Low Control Pin