Datasheet

7–154
A similar phenomenon occurs with respect to the V
CC
plane on a low-to-high transition, known as voltage output high, peak
or valley (V
OHP
, V
OHV
). Most problems are associated with a large V
OLP
because, in most cases, the range for a logic 0 is much
less than the range for a logic 1 (see Figure 23). For a comprehensive discussion of simultaneous switching, see the
Simultaneous Switching Evaluation and Testing application report or the Advanced CMOS Logic Designer’s Handbook
from TI.
The impact of these voltage noise spikes on a system can be extreme. The noise can cause loss of stored data, severe speed
degradation, false clocking, and/or reduction in system noise immunity. For an overview of how propagation delay is affected
by the switching of multiple outputs, please refer to the ac performance section of this report.
V
OL
V
IL
V
IH
V
OH
GND = 0
Permissible
Input Voltage Range
for Logic 1
Specified
Output Voltage Range
for Logic 1
Specified
dc Noise Margin
for Logic 1
Specified
dc Noise Margin
for Logic 0
Specified
Output Voltage Range
for Logic 0
Voltage
Output Input
Permissible
Input Voltage Range
for Logic 0
Noise
V
CC
or V
TT
Figure 23. dc Noise Margin
Simultaneous-Switching Solutions
IC manufacturers can reduce the effects of simultaneous switching by decreasing the inductance of the power pins, adding
multiple power pins, and controlling the turn on of the output. These techniques are described in detail in the 1988 Texas
Instruments Advanced CMOS Logic (ACL) Designer’s Handbook.
Octal devices employ the standard end-pin GND and V
CC
configuration while maintaining acceptable simultaneous switching
performance. Widebus series (16-, 18-, and 20-bit functions), on the other hand, are offered in an SSOP package (see the
packaging section of this report) that was developed by TI to save valuable board space and reduce simultaneous switching
effects. One might expect an increase in noise with 16 outputs switching in a single package; however, the simultaneous
switching performance is actually improved. There is normally a GND pin for every two outputs and a V
CC
pin for every four
outputs. This allows the transient current to be distributed across multiple power pins and decreases the overall current range
of change (di/dt) effect.
From basic circuit analysis, the induced voltage across an inductor is defined as:
v + L
ǒ
dińdt
Ǔ
Where:
L = Inductance
di/dt = Rate of change of the current
(12)