Datasheet

7–153
ac Performance
Simultaneous-Switching Phenomenon
System designers are frequently concerned with the performance degradation of ICs when outputs are switched. TI’s priority,
when designing the bus-interface families, is to minimize signal-integrity concerns and reduce the need for excess settling time
of an output waveform. This section addresses the simultaneous switching performance of these families for both octals and
Widebus devices.
Figure 21 shows a simple model of an output pin, including the associated capacitance of the output load and the inherent
inductance of the ground lead. The voltage drop across the GND inductor (V
L
) is determined by the value of the inductance
and the rate of change in current across the inductor. When multiple outputs are switched from high to low, the transient current
(di/dt) through the GND inductor generates a difference in potential on the chip ground with respect to the system ground. This
induced GND variation can be observed indirectly, as shown in Figure 22. The voltage output low, peak or valley (V
OLP
, V
OLV
),
is measured on one quiet output when all others are switched from high to low.
Q
i
V
O
C
L
V
L
+
–
Figure 21. Simultaneous-Switching Output Model
0
0
Volts – V
t – Time – ns
V
OLP
V
OHV
V
OHP
V
OLV
Figure 22. Simultaneous-Switching-Noise Waveform