Datasheet

7–152
Output Capacitance
TI designed both the CMOS and BiCMOS logic families for the lowest capacitance possible. GTL and BTL/FB, however, were
designed to meet a 5-pF I/O capacitance on the B port. Figure 20 shows the typical input, I/O, and output capacitance of
these families.
Input Capacitance
Capacitance – pF
LV LVC LVT LVT2 ALVC ABT ABT2 ABTE GTL FB CBT
†
†
Data is based on the input signal characteristics: V
IL
= 0 V, V
IH
= 3 V, t
r
/t
f
= 2 ns.
15
13.5
12
10.5
9
9.5
6
4.5
3
1.5
0
I/O Capacitance
Capacitance – pF
LV LVC LVT LVT2 ALVC ABT ABT2 ABTE GTL FB CBT
†
15
13.5
12
10.5
9
9.5
6
4.5
3
1.5
0
T
A
= 25°C,
V
CC
= 5 V (5-V families),
V
CC
= 3.3 V (3.3-V families),
V
IH
= 3 V,
V
IL
= 0 V,
All unused inputs are biased low
T
A
= 25°C,
V
CC
= 5 V (5-V families),
V
CC
= 3.3 V (3.3-V families),
V
IH
= 3 V,
V
IL
= 0 V,
All unused inputs are biased low
Figure 20. Capacitance Variation Between Families