Datasheet

7–151
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
8 Bit
8 Bit
16 Bit
Figure 18. Distributed Pinout of ’ABT16244A
When using the small-pin-count SSOPs (8-, 9-, and 10-bit functions), the same functionality will occupy less than half the
board area of an SOIC (70 mm
2
vs 165 mm
2
). There is also a height improvement over the SOIC that is beneficial when the
spacing between boards is a consideration. For very dense memory arrays, the packaging evolution has gone one step further
with the TSSOP. The TSSOP thickness of 1.1 mm gives a 58-percent height improvement over the SOIC. Another packaging
evolution is the EIAJ standard 100-pin TQFP package (0.5-mm lead pitch), which was developed for both the Widebus+
family (32-bit ABT) and the 18-bit FB+/BTL universal bus transceivers (UBT). The FB version is a high-power package.
A package cross-section, as shown in Figure 19, reveals a metal heatsink that facilitates the excellent thermal performance of
the package.
Heatsink
Die
Figure 19. Cross-Section of Thermally Enhanced EIAJ 100-Pin TQFP
For more information about the various packages used with the Advanced Bus-Interface families, refer to the Mechanical Data
section in the ABT or LVT data book.