Datasheet

7–150
Table 2. Θ
JA
for Different Packages
NO. OF PINS 14 16 20 24 48 52 56 64 80 100
SOIC
Package D D DW DW –– –– –– –– –– ––
SOIC
ΘJA 76 73 59 56 –– –– –– –– –– ––
SSOP
Package DB DB DB DB DL DL
SSOP
ΘJA 185 175 164 152 80 68
TSSOP
Package PW PW PW PW DGG DGG
TSSOP
ΘJA 195 187 143 140 115 92
QFP
Package RC PH
QFP
ΘJA 69 84
TQFP
Package PM PN PZ
TQFP
ΘJA 96 89 79
TQFP HP
Package PCA
TQFP
–
HP
ΘJA 52.4
Advanced Packaging
In addition to its strong commitment to provide fast, low-power, high-drive integrated circuits, TI is the clear-cut leader in logic
packaging advancements. The development of the SSOP in 1989 provided system designers the opportunity to reduce the
amount of board space required for bus-interface devices by 50 percent. Several 24-pin solutions, including the familiar SOIC,
SSOP, and TSSOP are widely used, as well.
The 48-/56-pin SSOP/TSSOP packages allow twice the functionality (16-, 18-, and 20-bit functions) in approximately the
same or less board area as a standard SOIC. This is accomplished by using a 25-mil (0.635-mm) lead pitch, as opposed to 50 mil
(1.27 mm) in SOIC. Figure 18 shows a typical pinout structure for the 48-pin SSOP/TSSOP. The flow-through architecture
is standard for all Widebus devices, making signal routing easier during board layout. Also, note the distributed GND and
V
CC
pins, which improve simultaneous switching performance, as discussed in the signal integrity section of this report.