Datasheet

7–149
24-pin SOIC
Area = 165 mm
2
24-pin SOIC
Height = 2.65 mm
Volume = 437 mm
3
Lead pitch = 1.27 mm
48-pin SSOP
Height = 2.74 mm
Volume = 469 mm
3
Lead pitch = 0.635 mm
48-pin SSOP
Area = 171 mm
2
24-pin SSOP
Area = 70 mm
2
Height = 2 mm
Volume = 140 mm
3
Lead pitch = 0.65 mm
24-pin SSOP
100-pin SQFP and
100-pin cavity TQFP
Area = 266 mm
2
100-pin SQFP
Height = 1.5 mm
Volume = 399 mm
3
Lead pitch = 0.5 mm
48-pin TSSOP
Area = 108 mm
2
48-pin TSSOP
Height = 1.1 mm
Volume = 119 mm
3
Lead pitch = 0.5 mm
24-pin SSOP
Area = 54 mm
2
Height = 1.1 mm
Volume = 59 mm
3
Lead pitch = 0.65 mm
24-pin TSSOP
Figure 17. Advanced Packages
A better understanding of the factors that contribute to junction temperature (T
J
) provides a system designer with more
flexibility when attempting to solve thermal issues. Device junction temperature is determined by equation 7:
T
J
+ T
A
)
(
Q
JA
P
T
)
Where:
T
J
= Junction (die) temperature (°C)
T
A
= Ambient temperature (°C)
Θ
JA
= Thermal resistance of the package from the junction to the ambient (°C/W)
P
T
= Total power of the device (W)
Junction temperature is altered by lower chip power consumption, longer trace length, heatsinks, forced air flow, package mold
compound, lead-frame size and material, surface area, and die size. Some of these are mechanically inherent in a particular
package, while others are controlled by the designer and are application specific. Understanding which variables can be
influenced by practicing good thermal-design techniques requires a more detailed investigation of power considerations as
well as thermal-resistance measurements. The package power dissipation is calculated using a junction temperature (T
J
) of
150°C and an ambient temperature (T
A
) of 55°C. Θ
JA
is calculated using a board trace length of 750 mils and no airflow. Table 2
provides the different Θ
JA
for different packages. Refer to the Package Thermal Considerations application report in the ABT
data book for the relationship between junction temperature and reliability.
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