Datasheet

7–134
5 V V
CC
2.5 V V
T
4.44 V V
OH
3.5 V V
IH
1.5 V V
IL
0.5 V V
OL
0 V GND
5-V CMOS
Rail-to-Rail 5 V
5-V TTL, ABT LVTTL, LVT,
LVC, ALVC, LV
ETL (ABTE)
Larger Noise Margins
BTL/FB+ GTL
5 V V
CC
1.5 V V
T
2.4 V V
OH
2 V V
IH
0.8 V V
IL
0.4 V V
OL
0 V GND
5 V V
CC
1.5 V V
T
2.4 V V
OH
1.6 V V
IH
1.4 V V
IL
0.4 V V
OL
0 V GND
3.3 V V
CC
1.5 V V
T
2.4 V V
OH
2 V V
IH
0.8 V V
IL
0.4 V V
OL
0 V GND
1.55 V V
T
2.1 V V
OH
1.62 V V
IH
1.47 V V
IL
1.1 V V
OL
1 V
0.8 V V
T
1.2 V V
OH
0.86 V V
IH
0.75 V V
IL
0.4 V V
OL
0 V
GN
D
Figure 1. Switching Standards With Guaranteed Thresholds
Input and Output Characteristics
In recent years, CMOS and BiCMOS logic families have further strengthened their position in the semiconductor market. New
designs have adopted both technologies in almost every system that exists, whether it is a PC, a workstation, or a digital switch.
However, when designing with such technologies, one must understand the characteristics of these families and the way inputs
and outputs behave in systems. It is very important for the designer to follow all rules and restrictions that the manufacturer
stipulates, as well as designing within the data sheet specifications. Since data sheets do not cover the input and output behavior
in detail, this section explains the input and output characteristics of CMOS, BiCMOS, GTL, and BTL/FB families.
Understanding the behavior of these inputs and outputs results in more robust designs and fewer reliability concerns.
CMOS and BiCMOS Input Characteristics
Both advanced CMOS (ALVC, LVC, and LV) and BiCMOS (ABT, LVT, GTL A port and FB A port) families have a CMOS
input structure. The input is an inverter consisting of a p-channel to V
CC
and an n-channel to GND, as shown in Figures 2 and 3.
When a low level is applied to the input, the p-channel transistor is ON and the n-channel is OFF, resulting in the current flowing
from V
CC
and pulling the node to a high state. When a high level is applied, the n-channel transistor is ON and the p-channel
is OFF and the current flows to GND, pulling the node low. In both cases, no current flows from V
CC
to GND. However, when
switching from one state to another, the input crosses the threshold region, causing the n-channel and the p-channel to be turned
on simultaneously, generating a current path between V
CC
and GND. This current surge can be damaging, depending on the
length of time that the input is in the threshold region (0.8 V to 2 V). The supply current (I
CC
) can rise up to several milliamperes
(mA) per input, peaking at approximately 1.5-V V
IN
(see Figure 4). However, this is not a problem when switching states at
the data-sheet-specified input transition time (see Table 1).