Datasheet

SCEA019 - January 2001
7–118 Texas Instruments GTLP Frequently Asked Questions
What are the advantages and disadvantages?
There is excellent signal integrity at higher frequencies, pullup-resistor termination draws less
power than totem-pole devices, there is no danger of bus contention on open-drain devices,
and the BIAS V
CC
pin provides for live insertion. The cost is two to three times higher than
FCT or LVT, but, because these TIER-3 solutions didn’t work, you need to move to a TIER-2
solution. Because you have so few cards, you could also consider a point-to-point solution
with LVDS or SERDES devices. They will provide higher data throughput with lower skew, but
at a higher cost. If you are comfortable with parallel single-ended devices, such as FCT, you
will be very comfortable designing with GTLP, which provides a cost-effective solution at this
performance node.
What devices would you recommend?
Use five SN74GTLPH16945GR (TSSOP) devices or two SN74GTLPH32945KR (LFBGA) and
one SN74GTLPH16945KR (VFBGA) medium-drive devices. The SN74GTLPH16945GR is
identical to the standard ’16245 (48-pin 2 x 8 bit bus transceiver), except for the BIAS V
CC
and V
ref
pins in place of two of the V
CC
pins. Out of the 80 possible bits, use 72 bits for the
buffer (DIR is fixed) and 8 bits for the 8-bit transceiver. The minimum R
TT
is 38 Ω for medium-
drive devices and that should be acceptable for this backplane loading. If an even lower
termination resistance is required to improve signal integrity or you need a slightly faster t
pd
,
the high-drive SN74GTLPH1645DGGR and/or the SN74GTLPH3245GKFR could be used.
These are 100-mA versions of the medium-drive (50 mA) GTLPH16945/32945, with an
edge-rate-control selection pin that allows for a slightly faster edge rate and reduced t
pd
.