Datasheet

SCEA019 - January 2001
7–114 Texas Instruments GTLP Frequently Asked Questions
32 Can I use GTLP as a low-voltage translator?
Bidirectional voltage translations between 3.3-V LVTTL and low-voltage CMOS (LV-CMOS)
are possible with GTLP devices. GTLP has a larger noise margin than general LV-CMOS
interface devices and can support shift-up level conversion through the use of active
transistors.
Two things must be considered:
• In the A-to-B (LVTTL to LV-CMOS) direction, V
ref
must be within 0.6 V of the termination
voltage because of the TI-OPC circuitry.
– TI-OPC circuitry is featured on most GTLP devices (except ’817, ’16612, and GTL
devices) and actively ports backplane energy to GND when the signal level is greater
than 0.7 V above V
ref
. This prevents large overshoots on improperly terminated or
unevenly loaded backplanes during low-to-high signal transitions, which limits the
subsequent undershoot that would reduce the upper noise margin. The TI-OPC
circuitry is integrated into the design and cannot be deactivated, but is inactive when
the B port is disabled. Except for the absolute maximum values, which must be met in
all cases, there are no V
TT
to V
ref
voltage-difference restrictions in the LV-CMOS to
LVTTL direction. Only in the LVTTL to LV-CMOS direction must V
ref
be set within
0.6 V of the termination voltage.
• The data-sheet recommended termination voltage is limited to 1.14 V minimum and
1.65 V maximum to correspond to GTL and GTLP standards. So, these recommended
data-sheet limits must be exceeded to translate at higher or lower voltages.
– The GTLP design team reviewed the TI SPICE simulations at voltages outside the
normal GTL/GTLP operating range and saw very little speed change when the
termination voltage is out of the normal range. There should be no degradation in
device reliability as long as the termination voltage does not exceed 2.75 V and the
recommended current limit is observed. However, TI’s policy is not to recommend
applications outside of data-sheet recommended limits. For some TI devices, we are
looking at expanding the GTLP data sheet dc limits to cover these level-translation
applications.
Table 10 shows the LV-CMOS device levels and possible voltage-translation combinations
using GTLP devices. The recommended GTLP device V
ref
settings for bidirectional and
unidirectional A-to-B cases are shown. Normally, V
ref
should be equal to the LV-CMOS
threshold voltage (V
t
), but it is adjusted to be within 0.6 V of the termination voltage V
CC
to
prevent activating TI-OPC circuitry in a steady-state condition.