Datasheet
SCEA019 - January 2001
Texas Instruments GTLP Frequently Asked Questions 7–97
To improve backplane performance, review the High-Performance Backplane Design With
GTL
+ application report, literature number SCEA011A, and Basic Design Considerations for
Backplanes application report, literature number SZZA016A.
Additional information on calculating backplane impedance can be found at
www.ultracad.com. There is detailed information on microstrip and stripline calculations and
an impedance calculator that can be downloaded.
15 What is the difference between synchronous clock and
source-synchronous clock?
Synchronous clock is an absolute clock in which each card receives the same clock signal at
exactly the same time. A clock generator with clock lines running to each card provides this
absolute clock. For the clock signal to arrive at each card at exactly the same time, the line
length must be exactly the same. For cards closer to the clock board, the lines are mitered
(run up and down, parallel to each other) to add distance to the line.
Source-synchronous clock is a relative clock. The driver card uses the incoming absolute
clock signal for timing, but all receiver cards use the clock sent from the driver card. Since the
driver card data and slightly delayed clock signal are sent at the same time, backplane length
or flight time is not a factor in timing calculations, unlike the absolute clock, which has to
account for the backplane length or flight time between the driver and receiver.
Additional information on source-synchronous operation was presented by Lee Sledjeski at
DesignCon 2000, in which he discussed private source-synchronous clocks for every 16 bits
of data to minimize delays due to device skew. The paper can be viewed at
http://www.fairchildsemi.com/products/backplane/designcon/lsdcon2k.pdf. These private
clocks can be implemented easily with the GTLPH16916 or the high-drive GTLPH1616; each
has one delayed buffered clock bit for every 17 bits of data. This paper also discusses
reducing the clock signal transmitted across the backplane by a factor of one-half as a way to
transfer data at the full system clock rate, i.e., data rate equals clock rate, which is 110 MHz.