Datasheet

SCEA019 - January 2001
Texas Instruments GTLP Frequently Asked Questions 7–91
GTLP
Transceiver
R
TT
ASIC or DSP
GTLP
Transceiver
Microstrip or
Stripline Trace
Connector
Figure 10. Heavily Loaded, Distributed-Capacitance Backplane Installation
GTLP devices allow higher frequencies on the backplane because of the improved
signal-integrity/incident-wave switching the results from the reduced swing (<1 V), lower slew
rate (0.35 V/ns to 0.5 V/ns), and matched termination resistors.
Additionally, GTLP fully supports live insertion, a capability that is imperative in
high-availability communications and networking applications. I
off
and PU3S provide hot-
insertion capability, while the BIAS V
CC
precharge circuitry precharges the B-port
input/outputs to the threshold voltage. This protects active data on the backplane from voltage
spikes or glitching, and provides true live-insertion capability.
GTLP devices are designed and manufactured in an advanced CMOS process that reduces
static-power consumption.
GTLP devices are 5-V tolerant because, although most applications are migrating to 3.3 V, or
lower, some existing circuits/devices on the board remain at 5 V.
GTLP is offered in a wide variety of packaging options and pinouts that are similar to
previous-generation devices. This helps simplify the designer’s task of migrating to a GTLP-
based backplane. High-drive devices are identical to the comparable medium-drive devices,
except for the addition of five ground, two V
CC
, and one edge-rate control (ERC) pins. The
additional ground and V
CC
pins reduce ground and V
CC
supply noise, thus providing
additional noise margin. The ERC pin allows the selection of either a slow or fast edge rate by
holding the control pin at V
CC
or ground. The faster edge rate reduces the propagation delay
and allows higher frequency operation in an optimally terminated backplane.