Datasheet
SCEA019 - January 2001
7–82 Texas Instruments GTLP Frequently Asked Questions
As shown in Figure 3, V
ref
is set by an R/2R resistor network between V
TT
and GND. The
resistor network maintains balanced upper and lower noise margins for any termination-
voltage fluctuations. A 0.1- to 0.01-µF bypass capacitor buffers voltage fluctuations and
should be as close to the V
ref
pin as possible.
V
ref
Figure 3. GTL R/2R Resistor Network
V
ref
is generated locally on each card, using size 805 1-kΩ and 2-kΩ ±1% resistors. Each
device V
ref
input takes, at most, 10 µA, so one resistor network per card is acceptable. The
card resistor network takes V
TT
from the backplane through a connector power pin. Do not
distribute the V
ref
power across all cards from one resistor network.