Datasheet

SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED AUGUST 2001
2–30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTL+ (unless otherwise noted) (see Figure 1)
MIN MAX UNIT
f
clock
Clock frequency 95 MHz
t
Pulse duration
LEAB or LEBA high 3.3
ns
t
w
P
u
lse
d
u
ration
CLKAB or CLKBA high or low 5.5
ns
A before CLKAB↑ 1.3
B before CLKBA↑ 2.3
t
Setu
p
time
A before LEAB↓ 0
ns
t
su
Set
u
p
time
B before LEBA↓ 1.3
ns
CEAB before CLKAB↑ 2.2
CEBA before CLKBA↑ 2.7
A after CLKAB↑ 1.6
B after CLKBA↑ 0.6
t
h
Hold time
A after LEAB↓ 4
ns
t
h
Hold
time
B after LEBA↓ 3.5
ns
CEAB after CLKAB↑ 1.1
CEBA after CLKBA↑ 0.9