Datasheet

7–67
Figure 14 shows simulation results for the GTL16612A operating at high clock rates of 80 MHz and 100 MHz. The innovative
design of the 18-bit device provides for extremely high throughput on a backplane if the timing requirements of the board can
be met.
Voltage – V
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Time – ns
25 30 35
40 45
0.2
80 MHz
100 MHz
Receiver in Slot 2
Figure 14. GTL16612A Simulation Results at 80 MHz and 100 MHz
Summary
The demonstration board has clarified backplane design issues and has provided unique insight into the capability of the GTL+
technology. With the escalation of requirements for high-speed data transfer, and a transition from low and medium
performance to high performance, the backplane will be a critical component in the performance equation. The TI GTL16622A
has served as a backplane driver for medium- and high-performance applications, while the new GTL16612A overcomes the
problems in a very high-performance backplane to provide good signal integrity. Clearly, GTL+ is the next-generation
technology, capable of accurately moving large amounts of data on the backplane with high speeds, while achieving the bit
rates that will be required by new designs.
Acknowledgment
The authors of this application report are Shankar Balasubramaniam, Ramzi Ammar, and Ernest Cox.
The authors recognize the contributions and assistance provided by Adam Ley, Gene Hintershcer, and Mac McCaughey.
References
1 Dr. Ed Sayre, Mr. Michael A. Baxter, NESA Inc., “An Innovative Distributed Termination Scheme for GTL Backplane Bus
Designs”, DesignCon 1998.
2 Texas Instruments, GTL/BTL: A Low Swing Solution for High Speed Digital Logic application report, literature number
SCEA003, September 1996.
3 Vantis, High Speed Board Design Techniques, August 1997.
4 Texas Instruments, SN74GTL16622A data sheet, literature number SCBS673.
5 California Micro Devices, “Termination Techniques for High Speed Buses”, Electronic Design News, February 1998.