Datasheet

7–65
The slot closest to the driver (slot 2) shows the worst-case ringing because it sees the fastest rise time of the IC driver compared
to the slots that are farther away from the driver. The worst-case signal at slot 2 also is due to the effect of reflected energy that
is maximum in the receiver closest to the driver.
3
Correlation
Figure 11 shows laboratory versus simulation results for the GTL16622A on the demonstration board. The results shown are
for the receiver at slot 2 (closest to the driver card). Here, as the frequency is increased, the time available for the data to be
sampled decreases, making good signal integrity necessary at these high frequencies.
30
Voltage – V
Time – ns
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
40 50 60 70 80
Time – ns
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
30 40 50 60 70
Driver in Slot 1
Receiver in Slot 2
Upper and Lower
Threshold Levels
2.0
Voltage – V
Driver in Slot 1
Receiver in Slot 2
Hardware Simulation
Figure 11. GTL16622A Signal Integrity (Hardware vs Simulation at 66 MHz)